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DATA SHEET
OM6213 48 x 84 pixels matrix LCD driver
Product specification File under Integrated Circuits, IC17 2001 Nov 07
Philips Semiconductors
Product specification
48 x 84 pixels matrix LCD driver
CONTENTS 1 2 3 4 5 6 7 7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 7.9 7.10 7.11 7.12 7.13 8 8.1 8.2 8.3 8.4 8.5 8.6 8.7 9 10 10.1 11 11.1 11.2 FEATURES APPLICATIONS GENERAL DESCRIPTION ORDERING INFORMATION BLOCK DIAGRAM PINNING PIN FUNCTIONS ROW 0 to ROW 47 row driver outputs COL 0 to COL 83 column driver outputs VSS1 and VSS2: negative power supply rails VDD1 to VDD3: positive power supply rails VLCDOUT, VLCDIN and VLCDSENSE: LCD power supplies VOS0 to VOS4 T1 to T7: test pads SDIN: serial data line SCLK: serial clock line D/C: mode select SCE: chip enable OSC: oscillator RES: reset BLOCK DIAGRAM FUNCTIONS Oscillator Address counter (AC) Display Data RAM (DDRAM) Timing generator Display address counter LCD row and column drivers VLCD generator INITIALIZATION ADDRESSING Data structure INSTRUCTIONS Reset function Function set 11.2.1 11.2.2 11.2.3 11.3 11.3.1 11.4 11.5 11.6 11.7 11.8 12 13 14 15 16 17 18 19 20 20.1 20.2 20.3 20.4 20.5 20.6 20.7 21 22 23 24 25 26 PD V H Display Control D, E Set Y address of RAM Set X address of RAM Temperature Control Bias value: VLCD generator
OM6213
TEMPERATURE COMPENSATION LIMITING VALUES HANDLING DC CHARACTERISTICS AC CHARACTERISTICS SERIAL INTERFACE RESET APPLICATION INFORMATION MODULE MAKER PROGRAMMING VLCD calibration Charge pump multiplication factor Bias system selected when BS[2:0] = 100 VLCD temperature coefficient selected when TC[1:0] = 01 (TC1) Seal bit Module Maker parameter programming Example of VLCD calibration flow CHIP INFORMATION BONDING PAD LOCATIONS DEVICE PROTECTION DIAGRAM TRAY INFORMATION DEFINITIONS LIFE SUPPORT APPLICATIONS
2001 Nov 07
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Philips Semiconductors
Product specification
48 x 84 pixels matrix LCD driver
1 FEATURES 2 APPLICATIONS
OM6213
* Single-chip LCD controller/driver * 48 row, 84 column outputs * Display data RAM 48 x 84 bits * On-chip: - Generation of LCD supply voltage (external supply also possible) - Generation of intermediate LCD bias voltages - Oscillator requires no external components (external clock also possible). * External reset (RES) input pin * Serial interface maximum 4.0 Mbit/s * CMOS compatible inputs * Mux rate: 1 : 48 * Logic supply voltage range VDD1 to VSS: 2.5 to 3.3 V * Supply voltage range for high voltage part VDD2 to VSS: 2.5 to 3.3 V * Display supply voltage range VLCD to VSS: 4.5 to 9.0 V * Low power consumption (typically 120 A), suitable for battery operated systems * Temperature compensation of VLCD * Temperature range: Tamb = -40 to +85 C * 5 Module Maker programmable parameters. 4 ORDERING INFORMATION
* Telecommunications equipment. 3 GENERAL DESCRIPTION
The OM6213 is a low power CMOS LCD controller driver, designed to drive a graphic display of 48 rows and 84 columns. All necessary functions for the display are provided in a single chip, including on-chip generation of LCD supply and bias voltages, resulting in a minimum of external components and low power consumption. The OM6213 interfaces to microcontrollers via a serial bus interface.
PACKAGE TYPE NUMBER NAME OM6213U TRAY chip with bumps in tray DESCRIPTION VERSION -
2001 Nov 07
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Philips Semiconductors
Product specification
48 x 84 pixels matrix LCD driver
5 BLOCK DIAGRAM
OM6213
handbook, full pagewidth
VDD1
VDD2
VDD3
COL 0 to COL 83 84 COLUMN DRIVERS
ROW 0 to ROW 47 48 ROW DRIVERS
VLCDIN
BIAS VOLTAGE GENERATOR DATA LATCHES
SHIFT REGISTER
VLCDSENSE VLCDOUT VSS1 VSS2 VOS [4:0] T1 T2 T3 T4 T5 T6 T7
VLCD GENERATOR
RESET DISPLAY DATA RAM (DDRAM) 48 x 84 bits
RES
OSCILLATOR
OSC
TIMING GENERATOR ADDRESS COUNTER DISPLAY ADDRESS COUNTER
DATA REGISTER
OM6213
I/O BUFFER
MGT840
SDIN
SCLK
D/C
SCE
Fig.1 Block diagram.
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Philips Semiconductors
Product specification
48 x 84 pixels matrix LCD driver
6 PINNING SYMBOL VOS4 VOS3 VOS2 VOS1 VOS0 VDD1 VDD3 VDD2 SCLK T7 SDIN D/C SCE OSC VSS2 T4 T5 T6 VSS1 7 7.1 PAD 3 4 5 6 7 13 to 18 19 to 22 23 to 30 31 32 to 35 36 to 39 40 41 42 43 to 50 51 52 53 54 to 61 DESCRIPTION VLCD offset pad 0 input VLCD offset pad 1 input VLCD offset pad 2 input VLCD offset pad 3 input VLCD offset pad 4 input supply voltage 1 supply voltage 3 supply voltage 2 serial clock input test 7 alternative HV-gen programming input serial data input and HV-gen programming input data/command input chip enable input (active LOW) oscillator input ground 2 test 4 input test 5 input test 6 output ground 1 7.5 RES ROW 11 to ROW 0 ROW 12 to ROW 23 COL 0 to COL 83 ROW 47 to ROW 36 ROW 24 to ROW 35 79 89 to 100 VLCDOUT VLCDSENSE 71 to 77 78
OM6213
SYMBOL T1 T2 T3 VLCDIN
PAD 62 63 64 65 to 70
DESCRIPTION test 1 output test 2 output test 3 output VLCD supply voltage input and HV-gen programming input VLCD generator output VLCD generator regulation input reset input (active LOW) LCD row driver outputs
101 to 112 LCD row driver outputs 113 to 196 LCD column driver outputs 197 to 208 LCD row driver outputs 209 to 220 LCD row driver outputs 1, 8 to 12, dummy pads 81 to 88, 221 and 222
PIN FUNCTIONS ROW 0 to ROW 47 row driver outputs
VLCDOUT, VLCDIN and VLCDSENSE: LCD power supplies
These pads output the row signals. 7.2 COL 0 to COL 83 column driver outputs
These pads output the column signals. 7.3 VSS1 and VSS2: negative power supply rails
If the internal VLCD generator is used, then all 3 pins must be connected together. If not (the internal VLCD generator is disabled and an external voltage is supplied at pin VLCDIN), VLCDOUT must be left open-circuit and VLCDSENSE must be connected to VLCDIN. VPR must be set to logic 0 to switch-off the charge pump if an external VLCD generator is used. VLCDIN is also used for HV-gen programming. 7.6 VOS0 to VOS4
VSS1 and VSS2 must be connected together, jointly referred to as VSS. When a pin has to be connected externally to VSS, VSS1 should be used. 7.4 VDD1 to VDD3: positive power supply rails
VDD1 provides the logic supply. VDD2 and VDD3 provide the analog supply; jointly referred to as VDD2. VDD2 and VDD3 must be connected together.
Five input pins for on-glass VLCD offset. Each pin must be connected to VSS1, which corresponds to logic 0, or to VDD1, which corresponds to logic 1. All five pins define a 5-bit two's complement number ranging from -16 to +15 decimal (from 10000 to 01111). The default value, with all pins connected to VSS1, is 0 decimal (00000). The register is refreshed by each set bias system command or when exiting the Power-down mode.
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Philips Semiconductors
Product specification
48 x 84 pixels matrix LCD driver
7.7 T1 to T7: test pads 8.3 Display Data RAM (DDRAM)
OM6213
In the application, T4, T5 and T7 must be connected to VSS. T1, T2, T3 and T6 must be left open-circuit. 7.8 SDIN: serial data line
Data line and HV-gen programming input. 7.9 SCLK: serial clock line
The OM6213 contains a 48 x 84 bit static RAM which stores the display data. The RAM is divided into 6 banks of 84 bytes (6 x 8 x 84 bits). During RAM access, data is transferred to the RAM via the serial interface. There is a direct correspondence between the X address and the column output number. 8.4 Timing generator
Input for the clock signal. 0 to 4.0 Mbits/s. 7.10 D/C: mode select
The timing generator produces the various signals required to drive the internal circuitry. Internal chip operation is not affected by operations on the data bus. 8.5 Display address counter
Input to select either command/address or data input. 7.11 SCE: chip enable The display is generated by continuously shifting rows of RAM data to the dot matrix LCD via the column outputs. The display status (all dots on/off and normal/inverse video) is set by bits D and E in the command `Display control' (see Table 2). 8.6 LCD row and column drivers
The enable pin allows data to be clocked in; this signal is active LOW. 7.12 OSC: oscillator
If the on-chip oscillator is used, this input must be connected to VDD1. If an external clock is used, it must be connected to pin OSC. If pin OSC is left at VSS1, the internal clock is disabled, the device is not clocked and the display may be left in a DC state. To avoid this, it is advisable to enter the Power-down mode before stopping the clock. 7.13 RES: reset
The OM6213 contains 48 rows and 84 column drivers, which connect the appropriate LCD bias voltages in sequence to the display in accordance with the data to be displayed. Figure 2 shows typical waveforms. Unused outputs should be left unconnected. 8.7 VLCD generator
This signal will reset the device and must be applied to properly initialize the chip; this signal is active LOW. 8 8.1 BLOCK DIAGRAM FUNCTIONS Oscillator
The voltage multiplier (i.e. charge pump) generates the VLCD voltage. The multiplication factor is Module Maker programmable (default value 4).
The on-chip oscillator provides the clock signal for the display system. No external components are required and the OSC input must be connected to VDD1. If an external clock signal is used, it must be connected to pin OSC. 8.2 Address counter (AC)
The address counter assigns addresses to the display data RAM for writing. The X address X[6:0] and the Y address Y[2:0] are set separately. After a write operation the address counter is automatically incremented by 1 according to the V flag.
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Philips Semiconductors
Product specification
48 x 84 pixels matrix LCD driver
OM6213
frame n
VLCD V2 V3 V4 V5 VSS1 VLCD V2 V3 V4 V5 VSS1 VLCD V2 V3 V4 V5 VSS1 VLCD V2 V3 V4 V5 VSS1
frame n + 1 Vstate1(t) Vstate2 (t)
ROW 0 R0 (t)
ROW 1 R1 (t)
COL 0 C0 (t)
COL 1 C1 (t)
VLCD V3 - VSS1 VLCD - V2 0V V3 - V2 V4 - V5 0V VSS1 - V5 V4 - VLCD - VLCD VLCD V3 - VSS1 VLCD - V2 0V V3 - V2 V4 - V5 0V VSS1 - V5 V4 - VLCD - VLCD
Vstate1(t)
Vstate2 (t)
0 1 2 3 4 5 6 7 8...
... 47 0 1 2 3 4 5 6 7 8...
... 47
MGT841
Vstate1(t) = C1(t) - R0(t) Vstate2(t) = C1(t) - R1(t) Fig.2 Typical LCD driver waveforms.
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Philips Semiconductors
Product specification
48 x 84 pixels matrix LCD driver
OM6213
DDRAM
bank 0 top of LCD R0
bank 1 R8
bank 2
R16
LCD
bank 3
R24
bank 4
R32
bank 5
R40
R47
MGT842
Fig.3 DDRAM to display mapping.
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Philips Semiconductors
Product specification
48 x 84 pixels matrix LCD driver
9 INITIALIZATION
OM6213
The address ranges are: X = 0 to 83 (1010011) and Y = 0 to 5 (101). Addresses outside these ranges are not allowed. In vertical addressing mode (V = 1) the Y address increments after each byte (see Fig.5). After the last Y address (Y = 5) Y wraps around to 0 and X increments to address the next column. In horizontal addressing mode (V = 0) the X address increments after each byte; see Fig.6. After the last X address (X = 83) X wraps around to 0 and Y increments to address the next row. After the very last address (X = 83 and Y = 5) the address pointers wrap around to address (X = 0 and Y = 0).
Immediately following power-on, all internal registers and the RAM content are undefined. A reset (RES) pulse must be applied. It should be noted that the device may be damaged if not properly reset. Reset is accomplished by applying an external RES pulse (active LOW) at pad RES. When reset occurs within the specified time, all internal registers are reset, however the RAM is still undefined. The state after reset is described in Section "Reset function". RES input must be 0.3VDD1 after VDD1 reaches VDD(min) (or higher) according to tVHRL timing (see Fig.16). 10 ADDRESSING Data is downloaded in bytes into the RAM matrix of the OM6213 as indicated in Figs.3, 4, 5 and 6. The display RAM has a matrix of 48 x 84 bits. The columns are addressed by the address pointer. 10.1 Data structure
handbook, full pagewidth
LSB
0
MSB 5
0
X address Y address
83
MGT843
Fig.4 RAM format, addressing.
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Philips Semiconductors
Product specification
48 x 84 pixels matrix LCD driver
OM6213
handbook, full pagewidth
0 1 2 3 4 5 0
6 7
0
Y address
503 X address 83
5
MGT844
Fig.5 Sequence of writing data bytes into RAM with vertical addressing (V = 1).
handbook, full pagewidth
0 84 168 252 336 420 0
1 85 169 253 337 421
2 86 170 254 338 422 X address 503 83
0
Y address
5
MGT845
Fig.6 Sequence of writing data bytes into RAM with horizontal addressing (V = 0).
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Philips Semiconductors
Product specification
48 x 84 pixels matrix LCD driver
11 INSTRUCTIONS The instruction format is divided into two modes. If D/C (mode select) is set LOW the current byte is interpreted as command byte (see Table 1). If D/C is set HIGH the following bytes are stored in the DDRAM. After every data byte the address counter is incremented automatically. The level of the D/C signal is read during the last bit of the data byte. Instructions can be sent in any order to the OM6213 (the exception being that the temperature control command must be followed by at least one byte of data or command). The MSB is transmitted first (see Fig.7). Figure 8 shows an example of a command stream, used to set-up the LCD driver. The serial interface is initialized when SCE is HIGH. In this state SCLK clock pulses have no effect and no power is consumed by the serial interface. A negative edge on SCE enables the serial interface and indicates the start of a data transmission. Figures 9 and 10 show the serial bus protocol.
OM6213
* When SCE is HIGH, SCLK clocks are ignored. During the HIGH time of SCE the serial interface is initialized (see Fig.11). * SDIN is sampled at the positive edge of SCLK * D/C indicates whether the byte is a command (D/C = 0) or RAM data (D/C = 1). It is read with the eighth SCLK pulse. * If SCE stays LOW after the last bit of a command/data byte, the serial interface expects bit DB7 of the next byte at the next rising edge of SCLK (see Fig.11) * A reset pulse with RES interrupts the transmission. The data being written into the RAM may be corrupted. The registers are cleared. If SCE is LOW after the rising edge of RES, the serial interface is ready to receive the D/C bit of a command/data byte (see Fig.12). * Instructions (except the temperature control command) are executed on the SCLK positive edge which latches DB0 and D/C * The temperature control command is executed on the SCLK positive edge which latches DB0 and D/C of the next command or the next write to the DDRAM (whichever occurs first).This command requires 2 bytes to be executed.
MSB handbook, halfpage (DB7) data
LSB (DB0) data
MGT639
Fig.7 General format of data stream.
handbook, full pagewidth
function set (H = 1)
bias system
set VPR
temperature control
function set (H = 0)
display control
Y address
X address
MGT846
Fig.8 Serial data stream, example.
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Philips Semiconductors
Product specification
48 x 84 pixels matrix LCD driver
OM6213
handbook, full pagewidth
SCE
D/C
SCLK
SDIN
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
MGT641
Fig.9 Serial bus protocol; transmission of one byte.
handbook, full pagewidth
SCE
D/C
SCLK
SDIN
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DB7 DB6 DB5
MGT642
Fig.10 Serial bus protocol; transmission of several bytes.
handbook, full pagewidth
SCE
D/C
RES
SCLK
SDIN
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DB7 DB6 DB5
MGT643
Fig.11 Serial bus reset function (SCE).
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Philips Semiconductors
Product specification
48 x 84 pixels matrix LCD driver
OM6213
handbook, full pagewidth
SCE
RES
D/C
SCLK
SDIN
DB7 DB6 DB5 DB4 DB3
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DB7 DB6 DB5 DB4
MGT644
Fig.12 Serial bus reset function (RES).
Table 1 Instruction set; see note 1 and Table 2 Instructions not expressly defined in Table 1 and reserved instructions must not be used in the application. INSTRUCTION (H = 0 or 1)
NOP Function set Write data
D/C
COMMAND BYTE DB7 0 0 D7 0 0 0 0 0 1 0 0 0 0 0 1 DB6 0 0 D6 0 0 0 0 1 X6 0 0 0 0 1 DB5 0 1 D5 0 0 0 0 0 X5 0 0 0 0 X DB4 0 0 D4 0 0 0 1 0 X4 0 0 0 1 X DB3 0 0 D3 0 0 1 X 0 X3 0 0 1 0 X DB2 0 PD D2 0 1 D X Y2 X2 DB1 0 V D1 1 X 0 X Y1 X1 DB0 0 H D0 X X E X Y0 X0
DESCRIPTION
0 0 1 0 0 0 0 0 0 0 0 0 0 0 0
no operation Power-down control; entry mode; extended instruction set control (H) writes data to display RAM.
(H = 0)
Reserved Reserved Display control Reserved Set Y address of RAM Set X address of RAM. reserved reserved sets display configuration reserved sets Y address of RAM; 0 Y 5 Sets X address part of RAM; 0 Y 5 reserved set temperature coefficient (TCx) reserved set bias system (BSx) reserved write VPR to register
(H = 1)
Reserved Temperature control Reserved Bias system Reserved Set VPR
VPR6 VPR5 VPR4 VPR3
0 1 X 1 TC1 TC0 X X X BS2 BS1 BS0 X X X VPR2 VPR1 VPR0
Note 1. X = don't care.
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Philips Semiconductors
Product specification
48 x 84 pixels matrix LCD driver
Table 2 Explanations for symbols in Table 1 BIT PD V H D, E LOGIC 0 chip is active horizontal addressing use basic instruction set display blank normal mode all display segments on inverse video mode VLCD temperature coefficient TCA Module Maker defined; VLCD temperature coefficient VLCD temperature coefficient TCC VLCD temperature coefficient TCD 11.2.3 H LOGIC 1
OM6213
chip is in Power-down mode vertical addressing use extended instruction set
TC1 and TC0
00 10 01 11 00 (TC0) 01 (TC1) 10 (TC2) 11 (TC3)
11.1
Reset function
After reset the LCD driver has the following state: * Power-down mode (PD = 1) * Horizontal addressing (V = 0) normal instruction set (H = 0) * Display blank (E = D = 0) * Address counter X[6:0] = 0, Y[2:0] = 0 * Temperature control mode (TC[1:0] = 0, TC0, TCA) * Bias system (BS[2:0] = 0) * VLCD is equal to 0, the HV-generator is switched off (VPR[6:0] = 0) * After power-on, RAM data is undefined * Oscillator off (external clock operation is possible). 11.2 11.2.1 Function set PD
When H = 0 the commands `display control', `set Y address' and `set X address' can be performed, when H = 1 the others can be executed. The commands `write data' and `function set' can be executed in both cases. 11.3 11.3.1 Display Control D, E
The bits D and E select the display mode (see Table 2). 11.4 Set Y address of RAM
Y2 to Y0 defines the Y address vector address of the display RAM; see Table 3. Table 3 Y2 0 0 0 0 1 1 11.5 Y address range Y1 0 0 1 1 0 0 Y0 0 1 0 1 0 1 CONTENT bank 0 bank 1 bank 2 bank 3 bank 4 bank 5
* All LCD outputs at VSS1 (display off) * Bias generator and VLCD generator off, VLCD can be disconnected * Oscillator off * Serial bus, command, etc. function * RAM contents not cleared; RAM data can be written.
Set X address of RAM
11.2.2
V
When V = 0, horizontal addressing is selected. The data is written into the DDRAM as shown in Fig.6. When V = 1, vertical addressing is selected. The data is written into the DDRAM as shown in Fig.5.
The X address points to the columns. The range of X is 0 to 83 (53H). 11.6 Temperature Control
The temperature coefficient of VLCD is selected by the two bits TC1 and TC0. 14
2001 Nov 07
Philips Semiconductors
Product specification
48 x 84 pixels matrix LCD driver
11.7 Bias value
OM6213
1 The bias voltage levels are set in the ratio of R - R - nR - R - R giving a ----------------- bias system. Different multiplex rates (n + 4) require different factors of `n' (see Table 4). This is programmed by BS[2:0]. For Mux 1 : 48 the optimum bias value `n' is given by n = Table 4 BS2 0 0 0 0 1 48 - 3 = 3.928 = 4 resulting in 18 bias.
Programming the required bias system BS1 0 0 1 1 0 BS0 0 1 0 1 0 n 7 6 5 4 - BIAS SYSTEM
1 1 11
RECOMMENDED MUX RATE 1 : 100 1 : 80 1 : 65 1 : 48 -
10 1 9 1 8
Module Maker programmable (see Table 11)
1 6 1 5 1 4
1 1 1 Table 5
0 1 1 LCD bias voltage SYMBOL V1 V2 V3 V4 V5 V6
1 0 1
2 1 0
1 : 24 1 : 18/1 : 16 1 : 10/1 : 9/1 : 8
BIAS VOLTAGE FOR 18 BIAS SYSTEM VLCD
7 6 2 1 8 8 8 8
x VLCD x VLCD x VLCD x VLCD VSS
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Philips Semiconductors
Product specification
48 x 84 pixels matrix LCD driver
11.8 VLCD generator
OM6213
The generated voltage at VLCD is dependent on the temperature, programmed temperature coefficient (TC) and the programmed voltage at the reference temperature (TCUT). V LCD = ( a + V OP x b ) x [ 1 + TC x ( T - T CUT ) ] (3) TCUT, a and b for each temperature coefficient are given in Table 6. The maximum voltage that can be generated is dependent on the voltage of VDD2 and the display load current. As the programming range for the internally generated VLCD allows values above the maximum allowed VLCD, the user has to ensure while setting the VPR register and selecting the Temperature Compensation (TC), that under all conditions and including all tolerances the VLCD limit of maximum 9 V will never be exceeded. For a particular liquid, the optimum VLCD can be calculated for a given multiplex rate. For a mux rate of 1 : 48, the optimum operating voltage of the liquid can be calculated as follows; 1 + 48 V LCD = ------------------------------------- V th = 6.06 V th 1 2 1 - ---------- 48 (4)
The binary number VOP representing the operating voltage can be set by the serial interface command and can be adjusted (calibrated) by 5 input pins according to the following formulae: (1) V OP = V OS + V CAL + ( 2 x V PR ) where: * VOP is an 8-bit unsigned number used internally for generation of the LCD supply voltage VLCD * VOS is a 5-bit two's complement number set by the 5 input pins VOS[4:0]; see Table 6 * VCAL is a 5-bit two's complement number set by the Module Maker; see Table 7 * VPR is a 7-bit unsigned number set by the serial interface command. To avoid numerical overflow the allowed values of VPR should be limited to the range VPR(min) to VPR(max) (decimal). The corresponding voltage at the reference temperature, TCUT, can be calculated as: V LCD ( Tcut ) = ( a + V OP x b ) (2)
where Vth is the threshold voltage of the liquid crystal used. Table 6 Typical values for parameters of the HV generator programming TCA 3.06 30.3 27 0 49 127 6.04 10.77 TCB 3.84 24.3 27 -0.87 20 101 4.81 8.74 TCC 3.62 26.1 27 -0.58 30 110 5.18 9.35 TCD 3.37 28.0 27 -0.29 39 120 5.56 10.11 UNIT V mV C 10-3/C decimal decimal V V
SYMBOL a b TCUT TC VPR(min) VPR(max) VLCD(min) VLCD(max)
VLCD(min) values are the values corresponding to VPR(min). VLCD(max) values are the theoretical values corresponding to VPR(max). Under all conditions and including all tolerances VLCD must never exceed 9 V. Example: VPR is set to 63 (decimal) and TCB is selected. At temperature TCUT the measured VLCD is 6.9 V. The user wants to decrease VLCD by 100 mV in order to set VLCD to 6.8 V. The best value for VOS is then -4 decimal (11100 binary in the two's complement notation). If VPR[6:0] is set to zero, the charge pump is turned off.
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Philips Semiconductors
Product specification
48 x 84 pixels matrix LCD driver
Table 7 VOS and VCAL values in two's complement notation DECIMAL 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 BINARY 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111
OM6213
DECIMAL -1 -2 -3 -4 -5 -6 -7 -8 -9 -10 -11 -12 -13 -14 -15 -16
BINARY 11111 11110 11101 11100 11011 11010 11001 11000 10111 10110 10101 10100 10011 10010 10001 10000
handbook, full pagewidth
MGT847
V LCD
b
a
00
01
02
03
04
05
06
...
...
FD
FE
FF
V OP
VOP 7 to 0 programming (00H to FFH). Depending on VPR restrictions defined in Table 6 and depending on VOS and VCAL, not all VOP[7:0] can be selected. If VPR is set to 0, the charge pump is turned off and VLCD = 0 V if no external VLCD supply is provided.
Fig.13 VLCD programming of the OM6213.
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Philips Semiconductors
Product specification
48 x 84 pixels matrix LCD driver
12 TEMPERATURE COMPENSATION
OM6213
Due to the temperature dependency of the liquid crystal viscosity, the LCD controlling voltage VLCD must be increased with lower temperature to maintain optimum contrast. Figure 14. shows VLCD for high multiplex rates. In the OM6213 the temperature coefficient of VLCD can be selected from 4 values (see Table 2) by setting bits TC[1:0].
handbook, full pagewidth
MGT848
VLCD
T
Fig.14 VLCD as a function of liquid crystal temperature (typical values).
13 LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 60134); see notes 1 and 2. SYMBOL VDD1 VDD2,3 VLCD Vi ISS II, Io Ptot Pout Tamb Tjun Tstg Notes 1. Stresses above those listed under Limiting Values may cause permanent damage to the device. 2. Parameters are valid over operating temperature range unless otherwise specified. All voltages are referenced to VSS1 unless otherwise noted. 14 HANDLING Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be totally safe, it is desirable to take normal precautions appropriate to handling MOS devices (see "Handling MOS devices"). PARAMETER logic supply voltage high supply voltage LCD supply voltage all input voltages ground supply current DC input or output current total power dissipation power dissipation per output ambient temperature junction temperature storage temperature -0.5 -0.5 -0.5 -0.5 -50 -10 - - -40 -65 -65 MIN. +6.5 +6.5 +10 VDD1 + 0.5 +50 +10 100 10 +85 +150 +150 MAX. V V V V mA mA mW mW C C C UNIT
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Philips Semiconductors
Product specification
48 x 84 pixels matrix LCD driver
OM6213
15 DC CHARACTERISTICS VDD1 = VDD2 = 2.5 to 3.3 V; VSS = 0 V; VLCD = 4.5 to 9.0 V; Tamb = -40 to +85 C; unless otherwise specified. SYMBOL VDD1 VDD2,3 VLCD IDD1 PARAMETER logic supply voltage high supply voltage LCD supply voltage total (VDD1 + VDD2 + VDD3) supply current 1 note 1 normal mode; VDD1 = VDD2 = VDD3 = 2.85 V; VLCD = 6.9 V (4 booster device); fSCLK = 0; Tamb = 25 C; display load = 10A; inputs at VDD1 or VSS, bias system 17; note 2 Power-down mode; with internal or external LCD supply voltage; inputs at VDD1 or VSS; note 3 VDD1 = VDD2 = VDD3 = 2.85 V; VLCD = 6.9 V; fSCLK = 0; Tamb = 25 C; display load = 10 A; inputs at VDD1 or VSS; bias system 17; notes 2 and 5 VDD1 = VDD2 = VDD3 = 2.85 V; VLCD = 6.9 V; fSCLK = 0; Tamb = 25 C; display load = 10 A; inputs at VDD1 or VSS; bias system 17; notes 2, 4 and 5 CONDITIONS MIN. 2.5 2.5 4.5 - TYP. - - - 120 MAX. 3.3 3.3 9.0 - UNIT V V V A
IDD2
supply current 2
-
3
-
A
IDD3
supply current external VLCD
-
20
-
A
ILCDIN
supply current from external VLCD
-
25
-
A
Logic VIL VIH ILI Ro(col) Ro(row) Vbias(col) Vbias(row) LOW-level input voltage HIGH-level input voltage input leakage current Vi = VDD1 or VSS note 6 note 6 VSS 0.7VDD1 -1 - - -100 -100 - - - 4 4 0 0 0.3VDD1 VDD1 +1 V V A k k mV mV
Column and row outputs column output resistance COL0 to COL83 row output resistance ROW0 to ROW47 bias tolerance COL0 to COL83 bias tolerance ROW0 to ROW47 VLCD tolerance internally generated note 7 20 20 +100 +100
LCD supply voltage generator VLCD(tol) -70 - +70 mV
2001 Nov 07
19
Philips Semiconductors
Product specification
48 x 84 pixels matrix LCD driver
Notes to the DC characteristics
OM6213
1. The maximum possible VLCD voltage that may be generated is dependent on voltage, temperature and (display) load. 2. Internal clock. 3. Power-down mode: during Power-down all static currents are switched off. 4. If external VLCD, the display load current is not transmitted to IDD. 5. VLCD external voltage applied to VLCDIN and VLCDSENSE inputs; VLCDOUT disconnected. VPR must be set to 0 to switch-off the charge pump. 6. Load current 10 A, outputs tested one at a time. 7. Valid for values of temperature, VOP and TC used at the calibration. 16 AC CHARACTERISTICS VDD1 = VDD2 = 2.5 V to 3.3 V; VSS = 0 V; VLCD = 4.5 to 9.0 V; Tamb = -40 to +85 C; unless otherwise specified. SYMBOL fclk(ext) fframe tVHRL tRW tR(op) PARAMETER external clock frequency frame frequency reset LOW pulse set-up time after power-on reset LOW pulse width end of reset pulse to interface being operational VDD1 = 3.0 V 10%; all signal timing is based on 20% to 80% of VDD and a maximum rise and fall time of 10 ns internal oscillator; note 1 notes 2 and 3; see Fig.16 see Fig.16 CONDITIONS MIN. 30.9 63 0 100 - TYP. 34.3 70 - - - MAX. 37.7 77 30 - 1000 UNIT kHz Hz s ns ns
Serial bus timing characteristics fSCLK clock frequency 0 - 4.00 MHz
Tcy(SCLK) tPWH1 tPWL1 tS2 tH2 tPWH2 tH5 tS3 tH3 tS4 tH4 Notes
clock cycle time SCLK SCLK pulse width HIGH SCLK pulse width LOW SCE set-up time SCE hold time SCE minimum HIGH time SCE start hold time D/C set-up time D/C hold time SDIN set-up time SDIN hold time note 4
250 100 100 60 100 100 100 100 100 100 100
- - - - - - - - - - -
- - - - - - - - - - -
ns ns ns ns ns ns ns ns ns ns ns
1. tframe = fclk(ext)/490. 2. RES may be LOW before VDD goes HIGH (see Fig.16). This is recommended. 3. Decoupling capacitor VLCD/VSS1 = 100 nF (higher capacitor size increases tVHRL or higher VDD1,2,3 reduces tVHRL). 4. tH5 is the time from the previous SCLK positive edge (irrespective of the state of SCE) to the negative edge of SCE (see Fig.15).
2001 Nov 07
20
Philips Semiconductors
Product specification
48 x 84 pixels matrix LCD driver
17 SERIAL INTERFACE
OM6213
handbook, full pagewidth
t S2
t H2
t PWH2
SCE t S3 D/C T cy(SCLK) t PWL1 SCLK t PWH1 t S2 t H3 (t H5 ) t H5
t S4 SDIN
t H4
MGT849
Fig.15 Serial interface timing.
18 RESET
handbook, full pagewidth
VDD1 t RW RES t RW
VDD1 t VHRL RES t R(op) SCE
MGT850
t RW
t RW
Fig.16 Reset timing.
2001 Nov 07
21
Philips Semiconductors
Product specification
48 x 84 pixels matrix LCD driver
19 APPLICATION INFORMATION Table 8 STEP D/C DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 1 2 Start 0 0 0 1 0 0 0 0 1 Example of OM6213 operation SERIAL BUS BYTE DISPLAY
OM6213
OPERATION SCE is going LOW function set; PD = 0, V = 0, select extended instruction set (H = 1 mode) set VPR; VPR is set to 16 function set; PD = 0, V = 0, select normal instruction set (H = 0 mode) display control; set normal mode (D = 1, E = 0) data write; Y and X are initialized to 0 by default, so they are not set here
3 4
0 0
1 0
0 0
0 1
1 0
0 0
0 0
0 0
0 0
5 6
0 1
0 0
0 0
0 0
0 1
1 1
1 1
0 1
0 1
MGS405
7
1
0
0
0
0
0
1
0
1
data write
MGS406
8
1
0
0
0
0
0
1
1
1
data write
MGS407
9
1
0
0
0
0
0
0
0
0
data write
MGS407
10
1
0
0
0
1
1
1
1
1
data write
MGS408
11
1
0
0
0
0
0
1
0
0
data write
MGS409
12
1
0
0
0
1
1
1
1
1
data write
MGS410
2001 Nov 07
22
Philips Semiconductors
Product specification
48 x 84 pixels matrix LCD driver
OM6213
SERIAL BUS BYTE STEP D/C DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 13 0 0 0 0 0 1 1 0 1 display control; set inverse video mode (D = 1, E = 1)
MGS412
DISPLAY
OPERATION
14
0
1
0
0
0
0
0
0
0
set X address of RAM; set address to 0000000
MGS412
15
1
0
0
0
0
0
0
0
0
data write
MGS414
The pinning of the OM6213 is optimized for single plane wiring e.g. for chip-on-glass display modules. Display size: 48 x 84 pixels.
handbook, full pagewidth
DISPLAY 48 x 84
24
84
24
OM6213
6 Cext I/O VDD VSS VLCD
MGT851
Fig.17 Application diagram.
The required minimum value for the external capacitors in an application with the OM6213 are: Cext = 100 nF (min.) for VLCD1,2/VSS1,2, Cext = 1.0 F (min.) for VLCD1,2,3/VSS1,2 Higher capacitor values are recommended for ripple reduction.
2001 Nov 07
23
Philips Semiconductors
Product specification
48 x 84 pixels matrix LCD driver
20 Module Maker programming The OM6213 features five Module Maker programmable parameters: 1. VLCD calibration 2. Charge pump multiplication factor 3. Bias system selected when BS[2:0] = 100 4. VLCD temperature coefficient selected when TC[1:0] = 01 (TC1) 5. Seal bit. Used to select the use of the default parameters or the Module Maker programmable parameters. Once set: a) The seal bit cannot be reset b) The Module Maker programmable parameters cannot be changed c) The Module Maker programmable parameters are selected and the default parameters are deselected. 20.1 VLCD calibration
OM6213
The first parameter calibrates the VLCD voltage. A 5-bit code (VCAL[4:0]) is used for this parameter. The code is implemented in two's complement notation giving rise to a positive or negative offset to the VPR register. VLCD calibration may be used together with VLCD offset (performed by connecting the VOS[4:0] pads to either VSS1 or to VDD1). VPR values must always be within the ranges specified in Table 6. V OP = V OS + V CAL + ( 2 x V PR ) (5) V LCD = a + V OP x b at T nom (6)
VLCD can be calculated from equations (5) and (6): a and b are parameters defined in Table 6. An example of the correspondence between the VCAL code and the relative VLCD calibration is shown in Table 9, where b is assumed to be 24.3 mV (TCB, temperature coefficient B) and VOS is assumed to be 0.
handbook, full pagewidth
VLCD offset: 5-bit signed value VOS [4:0] VLCD calibration: 5-bit signed value VCAL [4:0]
-16 to +15
-16 to +15
+
2
+
VOP
to high voltage generator
VPR register: 7-bit unsigned value VPR [6:0]
0 to +127
x
MGT852
Fig.18 VLCD offset and calibration
2001 Nov 07
24
Philips Semiconductors
Product specification
48 x 84 pixels matrix LCD driver
Table 9 VCAL codes and associated nominal calibration voltage (TCB, VOS = 0) VCAL 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 -1 -2 -3 -4 -5 -6 -7 -8 -9 -10 -11 -12 -13 -14 -15 -16 VLCD CALIBRATION (mV) (TCB, VOS = 0) 0 mV (default) +24.3 +48.6 +72.9 +97.2 +121.5 +145.8 +170.1 +194.4 +218.7 +243 +267.3 +291.6 +315.9 +340.2 +364.5 -24.3 -48.6 -72.9 -97.2 -121.5 -145.8 -170.1 -194.4 -218.7 -243 -267.3 -291.6 -315.9 -340.2 -364.5 -388.8 10 (TC2) 11 (TC3) 20.4 20.3
OM6213
Table 10 Charge pump multiplication factor definition MF 0 1 3 MULTIPLICATION FACTOR 4 (default)
VCAL[4:0] 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 11111 11110 11101 11100 11011 11010 11001 11000 10111 10110 10101 10100 10011 10010 10001 10000 20.2
Bias system selected when BS[2:0] = 100
The third parameter defines the bias system selected when BS[2:0] = 100. A 1-bit code (BS100) is used for this parameter. Table 11 Bias system selected when BS[2:0] = 100 definition BS 00 0 1
1 1 7 6
BIAS SYSTEM (default)
VLCD temperature coefficient selected when TC[1:0] = 01 (TC1)
The fourth parameter defines the VLCD temperature coefficient selected when TC[1:0] = 01 (TC1). TC1 may be defined by using a two bit code (TCx[1:0]). Table 12 VLCD temperature coefficient TC[1:0] 00 (TC0) 01 (TC1) 00 01 10 11 TC1[1:0] VLCD TEMPERATURE COEFFICIENT TCA TCB (default) TCA TCD TCC TCC TCD
Charge pump multiplication factor
The second parameter defines the charge pump multiplication factor. A 1-bit code (MF) is used for this parameter.
2001 Nov 07
25
Philips Semiconductors
Product specification
48 x 84 pixels matrix LCD driver
20.5 Seal bit
OM6213
The seal bit selects between the default parameters and the Module Maker programmed parameters. The seal bit prevents further changes to the Module Maker programmable parameters. A 1-bit code (SB) is used for this parameter. The seal bit, once set to 1, cannot be reset to 0. Table 13 Seal bit definition SB 0 1 20.6 defaults Module Maker programmable PARAMETERS MODULE MAKER PROGRAMMABLE PARAMETERS programming possible programming prevented
Module Maker parameter programming
Module Maker programmable parameters are stored in 10 non-volatile cells. Table 14 Non-volatile cell list CELL[9:0] 9 8 7 6 5 4 3 2 1 0 DESCRIPTION VCAL[4] VCAL[3] VCAL[2] VCAL[1] VCAL[0] MF BS100 TC1[1] TC1[0] SB
An unprogrammed cell contains 0. A programmed cell contains 1. OM6213 dice are shipped to the Module Maker with all cells unprogrammed (containing 0). An unprogrammed cell may be programmed by using the described procedure. A programmed cell cannot be unprogrammed to 0.
2001 Nov 07
26
Philips Semiconductors
Product specification
48 x 84 pixels matrix LCD driver
Table 15 Module Maker parameters programming procedure COMMAND BYTE STEP D/C DB7 DB6 DB5 DB4 DB3 DB2 DB1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Notes 1. Programming voltages are applied via pins SDIN and VLCDIN. 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 CELL[9] CELL[8] CELL[7] CELL[6] CELL[5] CELL[4] CELL[3] CELL[2] CELL[1] CELL[0] 0 0 0 1 0 0 0 0 0 DB0 switch power on reset the device (RES pulse) ACTION
OM6213
exit Power-down and set H = 0 instruction set wait 5 ms enter Power-down enter programming mode specify CELL[9] (VCAL[4]) specify CELL[8] (VCAL[3]) specify CELL[7] (VCAL[2]) specify CELL[6] (VCAL[1]) specify CELL[5] (VCAL[0]) specify CELL[4] (MF) specify CELL[3] (BS100) specify CELL[2] (TC1[1]) specify CELL[1] (TC1[0]) specify CELL[0] (SB) apply programming waveforms go back to step 7 if other cells need to be programmed (see note 5) exit programming mode switch power off
2. It is possible to program only one cell at a time. When applying programming waveforms, all cells (except the one being programmed) should be 0; see also example in note 5. 3. The seal bit (SB) must be the last to be programmed, since no further programming is possible when SB = 1. 4. If the seal bit is unprogrammed (SB = 0) the defaults (and not the Module Maker programmed parameters) are taken into account. 5. Example: a device has to be programmed to use a charge pump with a multiplication factor equal to 3 (initial state is MF = SB = 0, final state is MF = SB = 1). a) Execute steps 1 to 6. b) Set CELL[9:0] to 0000010000 (steps 7 to 16). c) Apply programming waveforms (step 17): MF cell is now programmed (MF = 1, SB = 0). d) Go back to step 7. e) Set CELL[9:0] to 0000000001 (steps 7 to 16). f) Apply programming waveforms (step 17): SB cell is now programmed (MF = SB = 1). g) Execute steps 18 to 20. 6. Programming waveforms MUST only be applied at step 17.
2001 Nov 07
27
Philips Semiconductors
Product specification
48 x 84 pixels matrix LCD driver
Table 16 Programming parameters SYMBOL VSDIN PARAMETER CONDITION MIN. 11 0 TYP. 11.5 -
OM6213
MAX. 12 VDD1 V V
UNIT
voltage applied to pin SDIN relative notes 1 and 3 to VSS1 programming active programming inactive
VLCDIN
voltage applied to pin VLCDIN relative to VSS1
notes 1 and 2 programming active programming inactive 9 0 - - 0 1 1 1 1 100 9.5 - 850 100 25 - - - - 120 10 VDD2 1000 200 40 - - 10 10 200 V V A A
oC
ILCDIN ISDIN Tamb(prog) tsu;SCLK th;SCLK tsu;SDIN th;SDIN tW Notes
current drawn by VLCDIN during programming current drawn by VSDIN during programming ambient temperature during programming set-up of internal data after last clock hold of internal data before next clock set-up of VSDIN prior to programming hold of VSDIN after programming pulse width of programming voltage
when programming a single bit to one
s s ms ms ms
1. The voltage drop across the ITO track and zebra connector must be taken into account to guarantee sufficient voltage at the chip pins. 2. The high voltage generator must be disabled (VPR = 0) when the VLCDIN pin is being driven. 3. Maximum voltage must never be exceeded (even for a short time). Care must be taken when applying the programming waveforms in order to avoid overshoots.
2001 Nov 07
28
Philips Semiconductors
Product specification
48 x 84 pixels matrix LCD driver
OM6213
handbook, full pagewidth
t su;SCLK
t h;SCLK
SCLK
SDIN DB1 DB0 t su;SDIN tW t h;SDIN DB7 DB6
VLCDIN
MGT853
Fig.19 Programming waveforms.
20.7
Example of VLCD calibration flow
The following tables are examples of the flow to calibrate VLCD. Table 17 VLCD calibration flow 1 COMMAND BYTE STEP 1 2 3 4 5 6 7 8 9 10 11 0 1 0 0 0 0 0 0 0 0 1 VPR6 VPR5 VPR4 VPR3 VPR2 VPR1 VPR0 0 0 0 1 0 0 0 0 1 D/C DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 switch power on reset the device (RES pulse) configure the device and fill in the DDRAM without switching the charge pump on exit Power-down and set H = 1 instruction set wait 5 ms set VPR and switch charge pump on measure VLCD switch charge pump off switch power off calculate VCAL[4:0] with look-up tables store VCAL[4:0] for programming later ACTION
2001 Nov 07
29
Philips Semiconductors
Product specification
48 x 84 pixels matrix LCD driver
Table 18 VLCD calibration flow 2 COMMAND BYTE STEP 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 D/C DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 switch power on ACTION
OM6213
reset the device (RES pulse) configure the device and fill in the DDRAM without switching the charge pump on exit Power-down and set H = 0 instruction set wait 5 ms enter programming mode CELL[9] specify CELL[9] (VCAL[4]) CELL[8] specify CELL[8] (VCAL[3]) CELL[7] specify CELL[7] (VCAL[2]) CELL[6] specify CELL[6] (VCAL[1]) CELL[5] specify CELL[5] (VCAL[0]) CELL[4] specify CELL[4] (MF) CELL[3] specify CELL[3] (BS100) CELL[2] specify CELL[2] (TC1[1]) CELL[1] specify CELL[1] (TC1[0]) 1 1 VPR0 specify CELL[0] = 1 (SB = 1) set H = 1 instruction set (exit programming mode) set VPR and switch charge pump on measure VLCD switch charge pump off if VLCD is not correct, go back to step 2 and try a different VCAL[4:0] switch power off store VCAL[4:0] for programming later
VPR6 VPR5 VPR4 VPR3 VPR2 VPR1
2001 Nov 07
30
Philips Semiconductors
Product specification
48 x 84 pixels matrix LCD driver
21 CHIP INFORMATION The OM6213 is manufactured in n-well CMOS technology. 22 BONDING PAD INFORMATION Table 19 Bonding pad information NAME Pad pitch Pad size, aluminium CBB opening Bump dimensions Wafer thickness (excluding bumps) ROW/COL SIDE 60 m (min.) 50 x 90 m (min.) 26 x 66 m (min.) 40 x 80 x 17.5 m (5) (min.) 381 m (25)
OM6213
INTERFACE SIDE 70 m (min.) 60 x 100 m (min.) 36 x 76 m (min.) 50 x 90 x 17.5 m (5) (min.)
handbook, halfpage
9.11 mm
handbook, halfpage
1.78 mm
OM6213
y center
pitch
100 m
y
x center
MGT855
x
MGT854
Fig.20 Bonding pads.
Fig.21 Shape of alignment mark (100 m diameter).
2001 Nov 07
31
Philips Semiconductors
Product specification
48 x 84 pixels matrix LCD driver
23 BONDING PAD LOCATION Table 20 Bonding pad location All x and y co-ordinates are referenced to the centre of the chip (dimensions in m; seeFig.22). COORDINATES SYMBOL Dummy pad Alignment VOS4 VOS3 VOS2 VOS1 VOS0 Dummy pad Dummy pad Dummy pad Dummy pad Dummy pad VDD1 VDD1 VDD1 VDD1 VDD1 VDD1 VDD3 VDD3 VDD3 VDD3 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 SCLK T7 T7 T7 T7 SDIN 2001 Nov 07 PAD x 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 -820 -810 -820 -820 -820 -820 -820 -820 -820 -820 -820 -820 -820 -820 -820 -820 -820 -820 -820 -820 -820 -820 -820 -820 -820 -820 -820 -820 -820 -820 -820 -820 -820 -820 -820 -820 y +4505 +4385 +4240 +4030 +3680 +3470 +3120 +2700 +2420 +2350 +2280 +2210 +2140 +2070 +2000 +1930 +1860 +1790 +1720 +1650 +1580 +1510 +1440 +1370 +1300 +1230 +1160 +1090 +1020 +950 +880 +670 +600 +530 +460 +390 32 SYMBOL SDIN SDIN SDIN D/C SCE OSC VSS2 VSS2 VSS2 VSS2 VSS2 VSS2 VSS2 VSS2 T4 T5 T6 VSS1 VSS1 VSS1 VSS1 VSS1 VSS1 VSS1 VSS1 T1 T2 T3 VLCDIN VLCDIN VLCDIN VLCDIN VLCDIN VLCDIN VLCDOUT VLCDOUT VLCDOUT VLCDOUT VLCDOUT PAD x 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 -820 -820 -820 -820 -820 -820 -820 -820 -820 -820 -820 -820 -820 -820 -820 -820 -820 -820 -820 -820 -820 -820 -820 -820 -820 -820 -820 -820 -820 -820 -820 -820 -820 -820 -820 -820 -820 -820 -820
OM6213
COORDINATES y +320 +250 +180 +110 -100 -310 -520 -590 -660 -730 -800 -870 -940 -1010 -1080 -1290 -1500 -1710 -1780 -1850 -1920 -1990 -2060 -2130 -2200 -2410 -2620 -2830 -3180 -3250 -3320 -3390 -3460 -3530 -3600 -3670 -3740 -3810 -3880
Philips Semiconductors
Product specification
48 x 84 pixels matrix LCD driver
OM6213
COORDINATES SYMBOL VLCDOUT VLCDOUT VLCDSEN RES Alignment Dummy pad Dummy pad Dummy pad Dummy pad Dummy pad Dummy pad Dummy pad Dummy pad ROW 11 ROW 10 ROW 9 ROW 8 ROW 7 ROW 6 ROW 5 ROW 4 ROW 3 ROW 2 ROW 1 ROW 0 ROW 12 ROW 13 ROW 14 ROW 15 ROW 16 ROW 17 ROW 18 ROW 19 ROW 20 ROW 21 ROW 22 ROW 23 COL 0 COL 1 PAD x 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 -820 -820 -820 -820 -810 -820 +825 +825 +825 +825 +825 +825 +825 +825 +825 +825 +825 +825 +825 +825 +825 +825 +825 +825 +825 +825 +825 +825 +825 +825 +825 +825 +825 +825 +825 +825 +825 +825 +825 y -3950 -4020 -4090 -4160 -4400 -4505 -4495 -4435 -4375 -4315 -4255 -4195 -4135 -3955 -3895 -3835 -3775 -3715 -3655 -3595 -3535 -3475 -3415 -3355 -3295 -3235 -3175 -3115 -3055 -2995 -2935 -2875 -2815 -2755 -2695 -2635 -2575 -2395 -2335 COL 2 COL 3 COL 4 COL 5 COL 6 COL 7 COL 8 COL 9 COL 10 COL 11 COL 12 COL 13 COL 14 COL 15 COL 16 COL 17 COL 18 COL 19 COL 20 COL 21 COL 22 COL 23 COL 24 COL 25 COL 26 COL 27 COL 28 COL 29 COL 30 COL 31 COL 32 COL 33 COL 34 COL 35 COL 36 COL 37 COL 38 COL 39 COL 40 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 SYMBOL PAD
COORDINATES x +825 +825 +825 +825 +825 +825 +825 +825 +825 +825 +825 +825 +825 +825 +825 +825 +825 +825 +825 +825 +825 +825 +825 +825 +825 +825 +825 +825 +825 +825 +825 +825 +825 +825 +825 +825 +825 +825 +825 y -2275 -2215 -2155 -2095 -2035 -1975 -1915 -1855 -1795 -1735 -1675 -1615 -1555 -1495 -1435 -1375 -1315 -1255 -1195 -1135 -1075 -1015 -955 -895 -835 -775 -595 -535 -475 -415 -355 -295 -235 -175 -115 -55 +5 +65 +125
2001 Nov 07
33
Philips Semiconductors
Product specification
48 x 84 pixels matrix LCD driver
OM6213
COORDINATES SYMBOL COL 41 COL 42 COL 43 COL 44 COL 45 COL 46 COL 47 COL 48 COL 49 COL 50 COL 51 COL 52 COL 53 COL 54 COL 55 COL 56 COL 57 COL 58 COL 59 COL 60 COL 61 COL 62 COL 63 COL 64 COL 65 COL 66 COL 67 COL 68 COL 69 COL 70 COL 71 COL 72 COL 73 COL 74 COL 75 PAD x 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 +825 +825 +825 +825 +825 +825 +825 +825 +825 +825 +825 +825 +825 +825 +825 +825 +825 +825 +825 +825 +825 +825 +825 +825 +825 +825 +825 +825 +825 +825 +825 +825 +825 +825 +825 y +185 +245 +305 +365 +425 +485 +545 +605 +665 +725 +785 +845 +905 +965 +1025 +1205 +1265 +1325 +1385 +1445 +1505 +1565 +1625 +1685 +1745 +1805 +1865 +1925 +1985 +2045 +2105 +2165 +2225 +2285 +2345 COL 76 COL 77 COL 78 COL 79 COL 80 COL 81 COL 82 COL 83 ROW 47 ROW 46 ROW 45 ROW 44 ROW 43 ROW 42 ROW 41 ROW 40 ROW 39 ROW 38 ROW 37 ROW 36 ROW 24 ROW 25 ROW 26 ROW 27 ROW 28 ROW 29 ROW 30 ROW 31 ROW 32 ROW 33 ROW 34 ROW 35 Dummy pad Dummy pad 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 SYMBOL PAD
COORDINATES x +825 +825 +825 +825 +825 +825 +825 +825 +825 +825 +825 +825 +825 +825 +825 +825 +825 +825 +825 +825 +825 +825 +825 +825 +825 +825 +825 +825 +825 +825 +825 +825 +825 +825 y +2405 +2465 +2525 +2585 +2645 +2705 +2765 +2825 +3005 +3065 +3125 +3185 +3245 +3305 +3365 +3425 +3485 +3545 +3605 +3665 +3725 +3785 +3845 +3905 +3965 +4025 +4085 +4145 +4205 +4265 +4325 +4385 +4445 +4505
2001 Nov 07
34
Philips Semiconductors
Product specification
48 x 84 pixels matrix LCD driver
OM6213
dummy pad alignment mark VOS4 VOS3 VOS2 VOS1 VOS0
dummy pad ROW 35
ROW 24 ROW 36
ROW 47 COL 83
dummy pad dummy pad VDD1 VDD3
VDD2 SCLK T7 SDIN D/C SCE OSC
COL 56 COL 55
y
0, 0
x
COL 28
T4 T5 T6
VSS1
T1 T2 T3
COL 0 ROW 23
VLCDOUT VLCDSEN RES alignment mark dummy pad
MGT856
ROW 11 dummy pad
Fig.22 Pad locations.
2001 Nov 07
35
. . .
VLCDIN
ROW 12 ROW 0
. . .
VSS2
COL 27
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
OM6213
Philips Semiconductors
Product specification
48 x 84 pixels matrix LCD driver
24 DEVICE PROTECTION DIAGRAM
OM6213
handbook, full pagewidth
VDD1
VDD2
VDD3
VSS1
VSS1 VSS2
VSS1
VSS2
VLCDIN, VLCDSENSE VSS1
VLCDOUT
VSS1
VSS1
VDD1
VLCDIN
T1, T2, T3, T6
VSS1
VSS1
VDD1
SDIN, T7
OSC, SCLK, SCE, RES, T4, T5, D/C, VOS [4:0] VSS1
VSS1
MGT858
The conditions for continuity test are as follows: Maximum forward current = 5 mA; Maximum reverse voltage = 5 V.
Fig.23 Device protection diagram.
2001 Nov 07
36
Philips Semiconductors
Product specification
48 x 84 pixels matrix LCD driver
25 TRAY INFORMATION
handbook, full pagewidth
OM6213
x
A G H
1,1 1,2 1,3 2,1 2,2 3,1 x,1
C
y
D B
F
1,y
x,y
A K L
,,,,,,, ,,,,,,,
E M SECTION A-A
A
J
MGT651
Fig.24 Tray details.
Table 21 Tray dimensions DIMENSION A B C D E F G H J K L M x y DESCRIPTION pocket pitch, x direction pocket pitch, y direction pocket width, x direction pocket width, y direction tray width, x direction tray width, y direction distance from cut corner to pocket (1 and 1) centre distance from cut corner to pocket (1 and 1) centre tray thickness tray cross section tray cross section pocket depth number of pockets in x direction number of pockets in y direction VALUE 14.45 mm 3.76 mm 9.31 mm 1.98 mm 50.8 mm 50.8 mm 10.95 mm 4.72 mm 3.96 mm 1.78 mm 2.44 mm 0.89 mm 3 12
handbook, halfpage
MGT857
The orientation of the IC in a pocket is indicated by the position of the IC type name on the die surface with respect to the chamfer on the upper left corner of the tray. Refer to the bonding pad location diagram for the orientating and position of the type name on the surface.
OM6213-1
Fig.25 Tray alignment.
2001 Nov 07
37
Philips Semiconductors
Product specification
48 x 84 pixels matrix LCD driver
26 DATA SHEET STATUS DATA SHEET STATUS(1) Objective data PRODUCT STATUS(2) Development DEFINITIONS
OM6213
This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Changes will be communicated according to the Customer Product/Process Change Notification (CPCN) procedure SNW-SQ-650A.
Preliminary data
Qualification
Product data
Production
Notes 1. Please consult the most recently issued data sheet before initiating or completing a design. 2. The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. 27 DEFINITIONS Short-form specification The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. 28 DISCLAIMERS Life support applications These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified.
2001 Nov 07
38
Philips Semiconductors
Product specification
48 x 84 pixels matrix LCD driver
NOTES
OM6213
2001 Nov 07
39
Philips Semiconductors - a worldwide company
Contact information For additional information please visit http://www.semiconductors.philips.com. Fax: +31 40 27 24825 For sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com.
(c) Koninklijke Philips Electronics N.V. 2001
SCA73
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
403506/01/pp40
Date of release: 2001
Nov 07
Document order number:
9397 750 07745

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